IBIS Macromodel Task Group

Meeting date: 11 January 2011

Members (asterisk for those attending):
Agilent:                    * Fangyi Rao
                            * Radek Biernacki
Ansoft:                       Chris Herrick
                              Danil Kirsanov
Ansys:                      * Samuel Mertens
                            * Dan Dvorjak
                              Deepak Ramaswamy
                              Jianhua Gu
Cadence Design Systems:       Terry Jernberg
                            * Ambrish Varma
Celsionix:                    Kellee Crisafulli
Cisco Systems:              * Mike LaBonte
                              Stephen Scearce
			      Ashwin Vasudevan
Ericsson:                   * Anders Ekholm
IBM:                          Greg Edlund
Intel:                      * Michael Mirmak
LSI Logic:                    Wenyi Jin
Mentor Graphics:            * John Angulo
                              Vladimir Dmitriev-Zdorov
                              Zhen Mu
                            * Arpad Muranyi
Micron Technology:          * Randy Wolff
Nokia-Siemens Networks:     * Eckhard Lenski
Sigrity:                      Brad Brim
                              Kumar Keshavan
                              Ken Willis
SiSoft:                     * Walter Katz
                              Mike Steinberger
                              Todd Westerhoff
ST Micro:                     Syed Sadeghi
Teraspeed Consulting Group: * Scott McMorrow
                            * Bob Ross
TI:                         * Casey Morrison
                            * Alfred Chong
Vitesse Semiconductor:        Eric Sweetman
Xilinx:                       Mustansir Fanaswalla

The meeting was lead by Arpad Muranyi

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Opens:

- None

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Call for patent disclosure:

- None

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Review of ARs:

- Arpad: Finish BIRDs
  - In progress

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New Discussion:

Arpad described changes made to the New Reserved Parameter BIRD

Arpad showed before and after versions of Typos_Format_Value_Default BIRD
- Some changes in tree descriptions
- Walter: This can be generalized
  - It doesn't matter if the name is reserved
- Radek: We can just just duplicate branch names are not allowed
- Arpad: Format, Value, Default are not branch names
- Ambrish: What is a reserved word here?
- Arpad: We can continue this discussion offline

- Arpad: It describes what is allowed for In, InOut, and Out usages
- Fangyi suggested a rewording
- Bob: We need to document exactly so the parser can check correctly
- Radek: 
- Fangyi: We should say explicitly what is allowed
- Walter: The EDA tool should ignore other items
- Arpad: It sounds like Walter disagrees
- Fangyi, Radek and Walter all agreed
- Bob: This is for the DLL, it is not checked
- Walter: This is for the AMI file
  - We also need to document for the DLL somewhere
- Radek: We must decide if the DLL can get a duplicate of the entire AMI string
- Bob: The question is if we should send the DLL undefined parameters
- Arpad: Walter and Bob seem to have opposing views
- Scott: There is no way to test DLLs
  - The inputs/outputs should be fully defined
  - All else should return an error
- Bob: That is my position
- Walter: An AMI test bench has been in place for years
  - Another way is to write a dummy checking DLL
- Scott: The DLL should return an error for anything unknown
  - Otherwise the DLL can have hidden functionality for competitive advantage
- Walter: There should be a BIRD for that
- Fangyi: Any param not in the AMI should not go to the DLL?
- Walter: Yes but that is not in the standard
  - The Opal spec covers this
  - There is a new reflector for discussing serdes back-channel
  - We could discuss new items there
- Arpad: Can we take the wording as is and amend later?
- Bob: The wording is good as is, but it is a matter of interpretation
- Walter: The DLL can't be expected to do anything with non-AMI file stuff
- Arpad: The tool can add nothing?
  - Can we agree to that?
- Walter: We can resolve it after some email discussion
- Arpad: Should it be an error for anything else to be passed
- Walter: Or it can ignore it
- Fangyi: That would allow too much ambiguity
  - Only IN and InOut params should be allowed
  - Another option is to allow Out too
- Walter: In or InOut would be good going in
  - And they must be there
- Bob: The EDA tool might add to the AMI file
- Walter: The AMI is only telling what the DLL allows
- John: Vendors must not use undocumented params
- Walter: Vendors do put invisible debug parameters in their DLLs
- Arpad: I will reword this section
  - Anyone can send suggestions
- Ambrish: I had suggestions in an email

Arpad showed an analog boundary definition presentation:
- Slide shows digital vs analog stimulus scenarios
- Scott: The analog device need to stimulate it must be within the model
  itself
- Arpad: Is the ideal PWL source sufficient?
- Scott: A PWL source is a triggered device
- Walter: All analog processing is done digitally
  - The DtoA input is a series of numbers
- Scott: 2 paradigms:
  - IBIS triggered source
    - Predriver boundary
    - That boundary is blurred in a serdes
  - This is an isolation amplifier
  - It isolates algorithmic from linear
- Arpad: The Opal doc shows sources with Vol/Voh parameters
- Walter: That is part of a circuit to generate a impulse response
  - The original IBIS spec lacked that
- Scott: The pulse going in is 1fs, a square wave
  - The s-param has everything needed to form the wave shape
  - If the model includes that s-param it is part of the model
  - It can be driven with a PWL source with close to 0 rise time
  - There has to be an isolation amp to have high impedance input
  - A digital data stream can be passed to this
- Arpad: How is the wave shape defined?
- Fangyi: Similarly, the IBIS V/T table defines wave shaping
- Walter: It works as long as the input is linear
- Arpad: Now we are saying the PWL is part of the tool
  - Where do the PWL params belong?
- Scott: 2 kinds of models
  - 1 Where everything is encapsulated in the model
    - Needs a fast input
  - 2 Part of the wave shape is done by the source
  - We can create models that work with either interface
    - Tr/Tf will say what wave shape to use
- Walter: People want to create general templates
  - SiSoft has no objection
  - Arpad wanted the template as an external 4 port circuit
  - That relies on the inputs being digital
- Arpad: No it is all analog
- Walter: In IBIS the input is digital
- Arpad: The model itself is always analog
  - It lends itself well to IBIS-ISS
- Bob: RC and s-param circuits are not equivalent
  - Some blocks shown here allow either
- Walter: We can generate an s-param from any IBIS-ISS circuit
  - IBIS measures rise time at the pad
  - This is at the input
  - I thought Tr/Tf had to be zero
  - That would crash some simulators
  - Impulse response is even more difficult
  - We can convert SPICE to ISS to create a fitted model
- Bob: We can agree they are not interchangeable models
- Walter: But they should give the same waveforms at the pad
- Arpad: I rearranged the block diagrams to show model boundaries
- Scott: they still have to specify the driving signal
- Arpad: There is a question if the 1 and -1 multipliers will work correctly
- Scott: The interface has to define high and low levels plus Tr/Tf
- Arpad: The WL wave shaping becomes questionable
- Scott: This model should have differential inputs
  - Today I need 2 separate buffer models
- Arpad: TX GetWave has a single output
- Walter: IBIS can only take 0 and 1
- Arpad: So TX GetWave drives the PWL?
- Walter: The negative source has to be created
  - Common model voltage is not handled yet
- Fangyi: There is no way to send TX GetWave output to an IBIS simulator
  - GetWave has only an impulse response for the channel
- Ambrish: The bottom figure is technically not possible
  - It is just a flow diagram
- Arpad: Walter said the input could come form GetWave
- Scott: It would have to be a processed GetWave with bits recovered
- Walter: No it is the analog output
- Scott: You can't have digital in one case and oversampled in another
- Walter: An ISS subckt can produce the right input
- Scott: OK, this is for an RX, not a TX
- Walter: Any simulator that handles ISS can get the waveform 2 ways
  - Kumar had that idea
  - Simulator have some difficulty doing it the same
- Bob: Is GetWave a voltage constrained waveform?
- Walter: It is an actual sampled waveform, any voltage
- Bob: They are typically centered around zero
  - If single ended is 0.5V the GetWave should put out -1V to 1V
- Walter: The 1 and -1 are not levels, they are amplification
- Arpad: What params do we need?
- Walter: Voh, Vol, Trf
- Arpad: The single GetWave output will have to match what the inputs expect
- Scott: The complimentary inputs will have to be created
- Arpad: We can't have two different sets of params
- Ambrish: Why do we need the bottom figure?
- Arpad: Walter said it is possible
- Walter: The top figure is just one way to generate an impulse response
- Arpad: I want to describe one analog model that can be used
- Casey: The discussion should be about generating an impulse response
- Walter: As long as we don't say this is THE way to do it
- Arpad: I'm still not sure what the analog model is
- Walter: Casey could you explain how to generate the s-params for this?
- Casey: I need guidance on incorporating the s-param into an analog model
  - Tools have to know how to work with it
- Walter: What subcircuit is needed from the EDA tool to generate step
  response?

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Next meeting: 18 Jan 2011 12:00pm PT

Next agenda:
1) BIRD 121-124 discussions

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IBIS Interconnect SPICE Wish List:

1) Simulator directives

